The present invention relates to an improvement in CMOS processing technology, whereby a masking step is saved.
Typically, CMOS processing requires at least four masking steps in addition to those used for NMOS processing, which imposes a great economic disadvantage on CMOS technology. The standard NMOS mask sequence is: (1) Moat (2) threshold-voltage ion implant (3) polysilicon (4) second contact (5) metal (6) POR (Protective Overcoat Removal). By contrast, the normal CMOS process requires at least four additional masks, as follows: (1) Tank (2) moat (3) channel stop (to do channel stopping only between N-channel devices) (4) threshold voltage ion implant (5) polysilicon (6) P+ (for low-sheet-resistance source/drain regions for P channel devices) (7) N+ (source/drain regions for N-channel devices) (8) second contact (9) metal (10) POR.
Thus, it is an object of the present invention to provide a more economical process for fabrication of CMOS devices.
It is a further object of the present invention to provide a process for fabrication of CMOS devices which reduces the number of masking steps required.
One possible way to save a masking step in CMOS processing might be to economize on the two separate masks normally required for the P-type and N-type source/drain regions. However, to do this successfully, it is necessary to find ways to obtain good control of both types of source/drain regions.
It is thus a further object of the present invention to provide a method for formation of both P-type and N-type source/drain regions using only one masking step, while retaining good control of the characteristics of the regions formed.
CMOS processes of varying complexity may be used for fabricating different types of devices. For example, the interconnect technology required for a memory array may be quite simple, whereas that required for a random logic structure (e.g., a microprocessor) may be more complex, and require additional patterned levels. Since acceptance of the simplest processes will also imply economic benefits for the more complex processes, a mask-saving scheme should preferably apply to any CMOS process, whether simple or complex.
It is thus a further object of the present invention to provide a mask-reduction scheme which applies to any CMOS process, whether simple or complex.